Kernel / Linux / 软件积累 · 2024年5月29日

PCIE 节点 DTS

&pcie0 {
//add by yu.chen for ethernet gpio power on
pinctrl-names = “ethernet-enable”;
pinctrl-0 = <&gpio_76>;
ethernet-gpios = <&ap_gpio 76 GPIO_ACTIVE_HIGH>;

sprd,pcie-startup-syscons =
    <&pmu_apb_regs 2 0
        REG_PMU_APB_RF_PWR_STATUS1_DBG
        MASK_PMU_APB_RF_PD_AP_SYS_STATE
        0x0>,
    <&aon_apb_regs 0 0
        REG_AON_APB_RF_PCIE_SLV_ADDR_OFFSET
        MASK_AON_APB_RF_PCIE_SLV_ADDR_OFFSET
        0x1>,
    <&aon_apb_regs 0 0
        REG_AON_APB_RF_PCIE_SLV_ADDR_OFFSET
        MASK_AON_APB_RF_PCIE_MOD_SEL
        0x10000>,
    <&anlg_phy_g2_regs 1 0
        REG_ANLG_PHY_G2_RF_ANALOG_PCIEPLL_H_PCIEPLLH_CTRL6
        0xf000  /* no corresponding macro */
        0xD000>,
    <&anlg_phy_g2_regs 0 0
        REG_ANLG_PHY_G2_RF_ANALOG_PCIE_GEN2_1T1R_REG_SEL_CFG_0
        MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_PCIE_GEN2_1T1R_PIPE_RESERVEDIN
        0x1>,
    <&anlg_phy_g2_regs 1 0
        REG_ANLG_PHY_G2_RF_ANALOG_PCIE_GEN2_1T1R_ANA_PCIE31_CTRL2
        MASK_ANLG_PHY_G2_RF_ANALOG_PCIE_GEN2_1T1R_PIPE_RESERVEDIN
        0x10000>,
    <&aon_apb_regs 0 0
        REG_AON_APB_RF_PHY_REF_CLK_EN
        MASK_AON_APB_RF_PCIE_PHY_REF_CLK_EN
        0x200>,
    <&pmu_apb_regs 0 0
        REG_PMU_APB_RF_PCIEPLL_H_REL_CFG
        MASK_PMU_APB_RF_PCIEPLL_H_FRC_OFF
        0x0>,
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_AHB_EB
        MASK_AP_IPA_AHB_RF_PCIE_SEL
        0x0>,
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_AHB_EB
        MASK_AP_IPA_AHB_RF_PCIE_AUX_EB
        0x40>,
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_AHB_EB
        MASK_AP_IPA_AHB_RF_PCIE_EB
        0x20>,
    <&pmu_apb_regs 0 0
        REG_PMU_APB_RF_PCIE_SLP_CFG
        MASK_PMU_APB_RF_PCIE_CLKREQ_PLL_GATE_MASK
        0x0>,
    <&pmu_apb_regs 0 150000
        REG_PMU_APB_RF_PCIE_SLP_CFG
        MASK_PMU_APB_RF_REG_PERST_N_ASSERT
        0x10>,
    <&pmu_apb_regs 0 2000
        REG_PMU_APB_RF_PCIE_SLP_CFG
        MASK_PMU_APB_RF_REG_PERST_N_ASSERT
        0x0>;

sprd,pcie-shutdown-syscons =
    <&pmu_apb_regs 0 0
        REG_PMU_APB_RF_PCIE_SLP_CFG
        MASK_PMU_APB_RF_REG_PERST_N_ASSERT
        0x10>,
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_AHB_EB
        MASK_AP_IPA_AHB_RF_PCIE_EB
        0x0>;

sprd,pcie-resume-syscons =
    <&pmu_apb_regs 2 0
        REG_PMU_APB_RF_PWR_STATUS1_DBG
        MASK_PMU_APB_RF_PD_AP_SYS_STATE
        0x0>,
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_AHB_EB
        MASK_AP_IPA_AHB_RF_PCIE_EB
        0x20>,
    /* WORKAROUND: only for orca + AQ */
    <&pmu_apb_regs 0 150000
        REG_PMU_APB_RF_PCIE_SLP_CFG
        MASK_PMU_APB_RF_REG_PERST_N_ASSERT
        0x10>,
    <&pmu_apb_regs 0 2000
        REG_PMU_APB_RF_PCIE_SLP_CFG
        MASK_PMU_APB_RF_REG_PERST_N_ASSERT
        0x0>;

sprd,pcie-suspend-syscons =
    <&pmu_apb_regs 0 0
        REG_PMU_APB_RF_PCIE_SLP_CFG
        MASK_PMU_APB_RF_REG_PERST_N_ASSERT
        0x10>,
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_AHB_EB
        MASK_AP_IPA_AHB_RF_PCIE_EB
        0x0>;

status = "okay";

};

&pcie1 {
sprd,pcie-startup-syscons =
<&ap_ipa_ahb_regs 0 0 REG_AP_IPA_AHB_RF_AHB_EB MASK_AP_IPA_AHB_RF_PCIE_AUX_EB 0x40>,
<&ap_ipa_ahb_regs 0 0 REG_AP_IPA_AHB_RF_AHB_EB MASK_AP_IPA_AHB_RF_PCIE_EB 0x20>,
<&aon_apb_regs 0 0 REG_AON_APB_RF_PCIE_SLV_ADDR_OFFSET MASK_AON_APB_RF_PCIE_SLV_ADDR_OFFSET 0x1>;

sprd,pcie-inta-assert-syscons =
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_PCIE_CTL0
        MASK_AP_IPA_AHB_RF_PCIE_SYS_INT_SW_EN
        0x1>;

sprd,pcie-inta-deassert-syscons =
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_PCIE_CTL0
        MASK_AP_IPA_AHB_RF_PCIE_SYS_INT_SW_EN
        0x0>;

sprd,pcie-shutdown-syscons =
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_AHB_EB
        MASK_AP_IPA_AHB_RF_PCIE_AUX_EB
        0x0>,
    <&ap_ipa_ahb_regs 0 0
        REG_AP_IPA_AHB_RF_AHB_EB
        MASK_AP_IPA_AHB_RF_PCIE_EB
        0x0>;

status = "disabled";

};

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